A collaborative effort between IBM, several European companies and universities, and the European Union has paid off, producing technologies that could improve chipmaking productivity by up to 30 per cent.

Speaking at DATE in Munich, IBM noted that the EU last year awarded $9.25m (€7m) to a consortium of three companies – rounded out with Infineon Technologies and STMicroelectronics -- and four universities with the purpose of encouraging the development and deployment of new tools and methodologies that will increase chip design productivity and reduce time to market.

The collaborative research effort -- known as Prosyd -- is centered around a specification language known as PSL and PSL-based tools and methodologies. PSL, based on the Sugar language from IBM, is a language for assertion specification and complex modeling.

According to IBM, the key result of the joint investment so far is in a collection of tools developed by the members of the consortium that interoperate around the emerging PSL standard. In particular, the IBM tools provide PSL-based solutions for chip verification, the firm said.

"The new IBM tools incorporate the use of the PSL standard, which together with advanced algorithms is opening up new directions in formal verification of larger designs," said Moshe Molcho, manager of IBM's Haifa Development Lab.

IBM will offer the tools, including the IBM DV RuleBase PE and IBM DV FoCs assertion compiler, in Europe through IBM Engineering & Technology Services (ET&S).

"We foresee ample innovations in chip design and verification made possible using the property-based design and verification techniques enabled by Prosyd," Dieter Muenk, general manager of E&TS for IBM in Europe. "This new offering demonstrates IBM’s continued commitment to serving our customers by rapidly bringing state-of-the-art design and verification technologies to the marketplace."