A lack of suitable design tools and the dominance of a design culture favouring synchronous design are the factors limiting the broader use of asynchronous, or clockless, technology in chips.

Asynchronous designs dispense with the global clock, and as a result offer advantages such as reduced power, since blocks are only active when needed, lower EMI, and better security. As a result they are often used in smartcard applications.

“The major disadvantage is that there are no design tools out there,” said Dr Georgios Theodoropoulos, a lecturer in the School of Computer Science at the University of Birmingham. “There is an [available] expertise to designing synchronous systems, while asynchronous… Once you remove the clock you end up with a parallel system, a concurrent system, and a non-deterministic one if you have arbiters and so on.”

An asynchronous smartcard chip from the European G3CARD project

Of the various alternative approaches to asynchronous design Theodoropoulos said a globally asynchronous, locally synchronous (GALS) methodology, whereby synchronous blocks communicate with each other asynchronously, has gained widest acceptance.

Theodoropoulos and Steve Furber’s advanced processor technologies group at the University of Manchester are developing methods for the formal verification of asynchronous designs using the Balsa language, which is based on Philips’ Tangram physical compiler and uses CSP process algebra. CSP links Balsa, formal verification, and simulation.

The Amulet3 processor

However, while simulation can guarantee correctness in synchronous designs, in asynchronous equivalents it cannot. For example, temperature changes might affect signal speed, which alters the order in which events happen and result in a deadlock.

“If you can have fast simulation you can try out more benchmarks and so do a better job of verification,” said Theodoropoulos.