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Silistix, an IP-bus and EDA startup originating from research performed by the
Most Asics and SOC architectures today are synchronous, with every component in the design functioning at the command of a single system clock. As process geometries continue to shrink and gate counts continue to climb, timing closure will become an increasingly difficult task, according to Silistix vice president of marketing David Fritz.
To get around clock-related problems, Silistix has introduced its asynchronous packet-based bus called CHAIN (an acronym somewhat inventively created from CHip-Area INterconnect). Users will specify the IP they want to use in their SOC and upload HDL blocks, then use Silistix's synthesis tools to generate a CHAIN bus that interconnects the blocks that make up the design.
"We can reduce design effort in a couple of significant ways," Fritz said. "Since there is no system clock coming into the interconnect and no critical path coming out of any of the endpoints into the interconnect and back out to another endpoint, timing closure becomes very simple. You get timing closure for each of your endpoints—an MPU, DSP, or memory-controller block—then timing closure on our CHAIN interconnect, which is simple because there is no system clock, and your timing closure is done. You don't have to worry about clock skew, clock balancing, or clock jitter. All those timing-related issues that pop up in the latter part of the design phase go away."
The technology was developed by John Bainbridge and Andrew Bardsley, both of whom received their PhDs under the tutelage of
While the company is talking about the CHAIN bus, it isn't disclosing details of its CHAINworks tool set until January.